Polar modulation is a technique used in a number of Radio Frequency (RF) transmitter architectures. Recently, it has found particular application in devices implementing the EDGE and 3G/UMTS telecommunication standards. Polar modulation is a combination of amplitude and phase modulation, which, instead of using in-phase and quadrature components as in quadrature modulation, uses the components of amplitude and phase. The modulation is performed separately for the amplitude and phase components, with the phase modulation typically performed using a Phase Locked Loop, PLL.
FIG. 1 is a schematic diagram of a transmitter (1) for implementing phase modulation (the components effecting amplitude modulation are not shown) and comprising a PLL (2) which in turn comprises a phase detector (3), a low pass filter (4), a voltage controlled oscillator VCO, (5), a divide-by-n divider (6) and a multi-modulus divider MMD (7). The phase modulation signal component (8) and a static RF channel selection signal (9) are summed at a summing unit (10a) and the result is fed into a sigma-delta modulator (10). By way of example, if the reference frequency (produced by the reference source (11)—see below) is 24 MHz and a carrier frequency of 2.4 GHz is required, the RF channel selection signal (9) is set to a value producing a divide ratio of 100 (at the MMD).
The sigma delta modulator (10) provides dithering for the input to the MMD, thus allowing (on average) a fractional divide ratio to be achieved. The specific dithering pattern also has a noise spectrum with energy concentrated at higher frequencies, which can be filtered by the low pass filter (4). The sigma-delta modulator signal is used to control the MMD (7), which divides the input signal by a value determined by the input from the sigma-delta modulator. The output of the MMD (7) is fed into the phase detector (3) which compares the output of the MMD with a reference signal (11a) generated by a crystal oscillator in the reference signal source (“reference clock”) (11). The phase detector (3) produces an output which is proportional to the difference in phase between its two inputs.
The output of the phase detector (3) is fed into the low pass filter (4) which might typically have a cut-off frequency in the region of a few hundred KHz. The low pass filter or loop filter has two distinct functions. A first function is the determination of loop dynamics, i.e. the range over which the loop can lock, the speed of locking and damping. A second function is the removal of spurious signals from the phase detector, such as ripple and higher harmonics. The low pass filtered signal representing the phase difference is then fed into the VCO (5). The VCO changes its output frequency according to this input. The phase modulated output of the PLL, with frequency divided by N, is then sent to an amplifier (12) and on to an antenna (13). The transmission frequency is therefore defined by both the factor N of the divide-by-N divider (6) and the average divide ratio of the MMD (7).
The divided output is fed back to the MMD (7). The MMD generates at its output a signal corresponding to the input from the divider (6), further divided by a value corresponding to the input from the sigma-delta modulator (10). This feedback mechanism drives the output signal of the MMD (7) to have the same frequency as the reference signal and to have a fixed phase with respect to that reference signal. Since the divide ratio applied by the MMD varies in proportion to the phase modulation signal (8), the MMD input signal, and hence the input signal to the amplifier (12), has a frequency that varies in order to achieve the desired phase modulation.
The arrangement of FIG. 1 provides for only a very limited bandwidth due to the low pass filtering in the PLL, e.g. a bandwidth on the order of a few hundred KHz. In order to provide for a wider bandwidth of operation, two-point modulation may be used. Two-point modulation introduces a second modulation point in the PLL and is illustrated in FIG. 2. The phase modulation signal component (8) is fed into a digital to analogue converter DAC (14), which controls the input to a second modulation point (15), this point being an input to the VCO (5). As with the input to the VCO from the low pass filter (4), the signal input to the second modulation point (15) changes the output frequency of the VCO. As the second modulation signal is not applied to the VCO via the low pass filter (4), it is not directly affected by that filter. However, there is a high pass filtering effect on the second modulation signal due to low frequency signals being removed by the feedback. High frequency signals are filtered out of the feedback loop by the loop filter and hence there is no cancelling of higher frequency signals at the VCO.
To complete the polar modulation effect, an amplitude modulation signal (16) is provided, which is fed to an AM Digital to Analogue converter (17). The output (18) of the AM Digital to Analogue converter then modulates the output of the PLL at the amplifier (12).
FIG. 3 is a graphical representation of signal (19) and frequency (20) of the idealized frequency response of the two-point modulator of FIG. 2, and illustrates the overall effect of the two modulation points. A first component (21) of the spectrum is that caused by the input from the sigma delta modulator (10) whilst a second component (22) is that caused by the input from the DAC (14). Fortuitously, the second component is essentially the inverse of the first component resulting in a constant frequency response (providing that there are no timing or gain mismatches) for the two-point polar modulator.
FIG. 4 is a schematic diagram of a practical implementation of a two-point polar modulator, showing the clocking arrangements. In order to ensure that there are no timing mismatches between the two modulation points, a single clock is used to control both signals (shown in FIG. 4 with broken lines). This clock signal is provided by an additional output (7a) of the MMD (7) which essentially is a clock signal running at the frequency of the reference signal source (11). The clock signal is passed to the phase modulator (23) via a divide-by-m divider (24) (this divider allows the phase modulator to be operated at a slower rate than the PLL reference signal source (11)). The phase modulator (23) also receives at a further input the bit stream that is to be transmitted.
In order to implement modulation schemes which require smooth phase transitions during a transmission symbol, it is necessary to operate the phase modulator (23) so as to output a sequence of relatively small phase changes, typically eight to sixteen per symbol period. It is thus necessary to clock the phase modulator (23) at a rate that is a multiple of the desired symbol rate. For example, to transmit symbols at a rate of 2 MS/Sec, the phase modulator (23) must be clocked at 16 MHz or more (assuming the divide ratio of divider 24 is set to unity). Achieving even higher symbol rates becomes difficult or even impossible due to the limitations of crystal frequencies and costs.